Recent Deforestation Pattern Changes (2000-2017) in the Central Carpathians:A Gray-Level Co-Occurrence Matrix and Fractal Analysis Approach

The paper explores the distribution of tree cover and deforested areas in the Central Carpathians in the central-east part of Romania, in the context of the anthropogenic forest disturbances and sustainable forest management. The study aims to evaluate the spatiotemporal changes in deforested areas due to human pressure in the Carpathian Mountains, a sensitive biodiverse European ecosystem. We used an analysis of satellite imagery with Landsat-7 Enhanced Thematic Mapper Plus (Landsat-7 ETM+) from the University of Maryland (UMD) Global Forest Change (GFC) dataset. The workflow started with the determination of tree cover and deforested areas from 2000–2017, with an overall accuracy of 97%. For the monitoring of forest dynamics, a Gray-Level Co-occurrence Matrix analysis (Entropy) and fractal analysis (Fractal Fragmentation-Compaction Index and Tug-of-War Lacunarity) were utilized. The increased fragmentation of tree cover (annually 2000–2017) was demonstrated by the highest values of the Fractal Fragmentation-Compaction Index, a measure of the degree of disorder (Entropy) and heterogeneity (Lacunarity). The principal outcome of the research reveals the dynamics of disturbance of tree cover and deforested areas expressed by the textural and fractal analysis. The results obtained can be used in the future development and adaptation of forestry management policies to ensure sustainable management of exploited forest areas

Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

International audienceThis paper presents a complex delta-sigma modu-lator (CDSM) designed for integration in a digital transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a DSM has the advantage of increased performance in terms of signal-to-noise-ratio in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the subsequent filtering stage. This constraint could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross coupling the in-phase (I) and quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross couplings from the I and Q quantizers outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30-dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient coarse/fine configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta sigma modulator (DSM), complex delta sigma modulator (CDSM), finite impulse response (FIR), multi-standard coexistence, digital transmitter

Digital RF Transmitter With Single-Bit ΔΣ\Delta\Sigma M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

International audienceThis paper presents a single-bit RF transmitter based on single-bit switched-capacitor RF digital-to-analog converters (DACs) embedded in an finite-impulse response (FIR) filter (FIR-DACs). The transmitter system comprises a single-bit quadrature delta-sigma modulator (M), a digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete-and continuous-time filtering. The on-chip part of the FIR-DAC is built exclusively with CMOS inverters and metal-oxide-metal capacitors, which are implemented in the interconnect layers to propose a compact fully digital solution, suitable for advanced CMOS nodes. A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete-and continuous-time filtering, the out-of-band quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in a 28-nm FD-SOI CMOS technology with ten metal layers and occupies a total active area of only 0.047 mm 2. The overall power consumption is 38 mW at 4.6-dBm peak output power, 900-MHz carrier frequency, and 1-V supply. FD-SOI body bias V t tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise high-frequency I/Q interleaving, which enables high image and local oscillator rejections. The resulting power consumption, surface, and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications. Index Terms-28-nm FD-SOI, all-digital transmitter, body bias, delta-sigma modulation (M), finite-impulse response filter (FIR), finite-impulse response digital-to-analog converter (FIR-DAC), switched-capacitor (SC) DAC